This invention relates to a method for making complementary MOS semiconductors (referred to as CMOS hereafter) and, more particularly, to a method for making silicon on sapphire (SOS) semiconductors.
In general, CMOS, which is provided in an isolated semiconductive layer on an insulative substrate, has p channel and n channel MOS transistors which have high density drain regions in contact with each other at the boundary of the p channel and n channel transistors. This kind of CMOS is made using the following method.
As shown in FIG. 1, after a semiconductive layer 2 is provided on an insulative substrate 1, such as sapphire, gate electrodes 41, 42 of polycrystal silicon are provided on gate oxide layers 31, 32, respectively. Next impurities with a small diffusion coefficient are selectively implanted by ion implantation, for instance using arsenic for the n channel transistor and boron for the p channel transistor. And then, source region 51 and drain region 61 of n+ type and source region 52 and drain region 62 of p+ type are provided by activation treatment, respectively.
In this CMOS, the element area of the transistor may be considerably minimized because the high density drain regions 61, 62 of the n channel transistor and the p channel transistor contact each other at the boundary of the transistors. However, if the source region 51 and the drain region 61 of n channel transistor are provided by ion implantation (or thermal diffusion) of arsenic, the arsenic sometimes does not reach the boundary between the semiconductive layer 2 and insulative substrate 1. So, if the CMOS is used as an inverter, leakage current occurs shown by a dotted line in FIG. 1. That is, if the input (Vin) is biased at a level "L" and the output (Vout) is at level "H" when the p channel transistor is in the "ON" condition, there will be a leakage current from the drain region 62 of the p channel transistor to the source region 51 of the n channel transistor because a forward bias condition will exist between them.
In order to eliminate the above defect, the CMOS shown in FIG. 2 has been used. That is, the source regions 51' 52' and the drain regions 61', 62' of n channel and p channel transistors are so provided in the isolated semiconductive layer 2 that these regions 51', 52', 61', and 62' extend to the boundary between the layer 2 and the insulative substrate 1, in order to prevent any leakage current. However, this CMOS device exhibits the short channel effect because the channel length (Leff) is extremely short.
Alternatively, the source region and drain region can be so provided that they extend to the boundary between the layer and the substrate by minimizing the thickness of the layer thereby eliminating the short channel effect. But the thin semiconductive layer deteriorates crystallinity of the semiconductive layer, and bad crystallinity is deleterious to electrical and other characteristic of the transistor when minimizing the transistor area.
Another method for making COS has been employed in order to prevent the short channel effect and leakage current.
Referring to FIG. 3A, after a semiconductor layer, such as a silicon layer, is grown on an insulative substrate 11 by epitaxial growth, the semiconductive layer is selectively removed so that a semiconductive layer 12 is provided on substrate 11. Arsenic ions and boron ions are implanted in the semiconductive layer 12 in order to make a P-channel transistor area and an N-channel transistor area respectively. And, after gate electrodes 14.sub.1, 14.sub.2 are provided on gate oxide layers 13.sub.1, 13.sub.2, resist patterns 15 are provided to cover the semiconductive layer of the p channel transistor area by photolithography, and a first shallow arsenic ion implantation layer 16 is provided below the surface of the layer 12 by selectively implanting arsenic ions in the layer 12 using resist patterns 15 and electrode 14.sub.1 as a mask.
Referring to FIG. 3B, the resist patterns 15 are removed, and resist patterns 17 are provided to cover the semiconductive layer 12 of the p channel transistor area and a portion of layer 12 near electrode 14.sub.1. A second deep arsenic ion implantation layer 18 is provided by selectively implanting arsenic ions in layer 12 with high implantation energy using the resist patterns 17 as a mask.
Next, referring to FIG. 3C, the resist patterns 17 are removed, and resist patterns 19 are provided to cover the semiconductive layer of an n channel transistor area by photolithography. A first shallow boron ion implantation layer 20 is provided below the surface of the layer 12 by selectively implanting boron ion in the layer with low implantation energy using resist patterns 19 and electrode 142 as a mask.
Referring now to FIG. 3D, the resist patterns 19 are removed, and resist patterns 21 are provided to cover layer 12 of the n channel transistor area and a portion of layer 12 near the electrode 14.sub.2 by photolithography. A second deep boron ion implantation layer 22 is provided by selectively implanting boron ions in the layer 12 with high implantation energy using the resist pattern 21 as a mask.
Then, referring to FIG. 3E, the resist patterns 21 are removed and the CMOS device is heat treated. As a result, the first and second arsenic layers 16, 18 are activated, and source and drain regions 23.sub.1, 24.sub.1 of n+ type are provided, each of which is shallow near electrode 14.sub.1 but deep as it extends to a boundary between layer 12 and substrate 11 farther from electrode 14.sub.1. Source and drain regions 23.sub.2, 24.sub.2 of p+ type also are provided, each of which is shallow near electrode 14.sub.2 but deep as it extends to the boundary between layer 12 and substrate 11 farther from the electrode 14.sub.2. So, the CMOS device has drain regions 24.sub.1, 24.sub.2 of n+ type and p+ type which contact each other over the entire boundary between the n channel and p channel transistors. This CMOS eliminates the leakage current and the short channel effect, as described above. But, the above described process is more complex than the ordinary CMOS process, because it requires the photolithography process and ion implantation process to each be repeated.